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NONVOLATILE LOGIC CIRCUIT, AN INTEGRATED CIRCUIT INCLUDING THE NONVOLATILE LOGIC CIRCUIT AND A METHOD OF OPERATING THE INTEGRATED CIRCUIT, CAPABLE OF REDUCING A BOOSTING TIME
NONVOLATILE LOGIC CIRCUIT, AN INTEGRATED CIRCUIT INCLUDING THE NONVOLATILE LOGIC CIRCUIT AND A METHOD OF OPERATING THE INTEGRATED CIRCUIT, CAPABLE OF REDUCING A BOOSTING TIME
PURPOSE: A nonvolatile logic circuit, an integrated circuit including the nonvolatile logic circuit and a method of operating the integrated circuit are provided to reduce the frequency of a writing operation in consideration of durability . ;CONSTITUTION: A latch unit(11) has first and second latch nodes(LN1,LN2). The latch unit comprises first and second PMOS transistors(P1,P2). An inverter(14) inverts reversely input data. A transmission unit(15) comprises first and second transmission units(151,152) The first and second transmission units are controlled by a read enable signal. A writing selection unit(16) applies current to first and second nonvolatile memory cells(12,13) in opposite direction. A reading selection unit(17) provides data stored in a nonvolatile memory cell to the latch node. An equalizer(18) equalizes the voltage of the latch node.;COPYRIGHT KIPO 2011
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