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NONVOLATILE LOGIC CIRCUIT, AN INTEGRATED CIRCUIT INCLUDING THE NONVOLATILE LOGIC CIRCUIT AND A METHOD OF OPERATING THE INTEGRATED CIRCUIT, CAPABLE OF REDUCING A BOOSTING TIME

机译:非易失性逻辑电路,包括非易失性逻辑电路的集成电路以及操作该集成电路的方法,该方法可减少启动时间

摘要

PURPOSE: A nonvolatile logic circuit, an integrated circuit including the nonvolatile logic circuit and a method of operating the integrated circuit are provided to reduce the frequency of a writing operation in consideration of durability . ;CONSTITUTION: A latch unit(11) has first and second latch nodes(LN1,LN2). The latch unit comprises first and second PMOS transistors(P1,P2). An inverter(14) inverts reversely input data. A transmission unit(15) comprises first and second transmission units(151,152) The first and second transmission units are controlled by a read enable signal. A writing selection unit(16) applies current to first and second nonvolatile memory cells(12,13) in opposite direction. A reading selection unit(17) provides data stored in a nonvolatile memory cell to the latch node. An equalizer(18) equalizes the voltage of the latch node.;COPYRIGHT KIPO 2011
机译:目的:提供一种非易失性逻辑电路,一种包括该非易失性逻辑电路的集成电路以及一种操作该集成电路的方法,以考虑到耐用性来降低写入操作的频率。 ;组成:锁存器单元(11)具有第一和第二锁存器节点(LN1,LN2)。锁存单元包括第一和第二PMOS晶体管(P1,P2)。反相器(14)将反向输入的数据反相。传输单元(15)包括第一和第二传输单元(151,152)。第一和第二传输单元由读取使能信号控制。写入选择单元(16)以相反的方向向第一和第二非易失性存储单元(12,13)施加电流。读取选择单元(17)将存储在非易失性存储单元中的数据提供给锁存节点。均衡器(18)均衡闩锁节点的电压。; COPYRIGHT KIPO 2011

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