首页> 外国专利> VARIABLE DELAY CIRCUIT, MEMORY CONTROL CIRCUIT, DELAY AMOUNT SETTING APPARATUS, DELAY AMOUNT SETTING METHOD AND COMPUTER READABLE RECORDING MEDIUM RECORDING DELAY AMOUNT SETTING PROGRAM

VARIABLE DELAY CIRCUIT, MEMORY CONTROL CIRCUIT, DELAY AMOUNT SETTING APPARATUS, DELAY AMOUNT SETTING METHOD AND COMPUTER READABLE RECORDING MEDIUM RECORDING DELAY AMOUNT SETTING PROGRAM

机译:可变延迟电路,存储器控制电路,延迟量设置装置,延迟量设置方法和计算机可读记录介质记录延迟量设置程序

摘要

(assignment) ; It is an object to set a wide range of delays from a signal input to an output while suppressing the circuit scale. ; (Solution) ; A variable delay circuit 100 capable of changing the delay amount from the input of the signal IN to the output thereof, comprising: a first delay portion 101 for delaying the signal IN by a first delay amount and a signal IN; Second delay unit 102 for delaying c) by a second delay amount larger than the first delay amount, and when the delay amount exceeds the maximum delay amount that can be delayed by the first delay unit 101, the delay amount is zero. And a delay amount selector 103 for selecting a signal path that is the sum of the first delay amount and the second delay amount.
机译:(转让);一个目的是在抑制电路规模的同时,设置从信号输入到输出的宽范围的延迟。 ; (解决方案);可变延迟电路100,其能够将延迟量从信号IN的输入改变为信号IN的输出,包括:第一延迟部101,用于将信号IN延迟第一延迟量和信号IN。第二延迟单元102用于将c)延迟第二延迟量,该第二延迟量大于第一延迟量,并且当该延迟量超过第一延迟单元101可以延迟的最大延迟量时,该延迟量为零。延迟量选择器103用于选择作为第一延迟量和第二延迟量之和的信号路径。

著录项

  • 公开/公告号KR101082748B1

    专利类型

  • 公开/公告日2011-11-10

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20080092358

  • 发明设计人 야마자키 마나부;

    申请日2008-09-19

  • 分类号G11C11/407;G11C11/4093;G11C11/4096;

  • 国家 KR

  • 入库时间 2022-08-21 17:49:32

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