Parallel adder-subtractor in the ternary numeral system on neurons

摘要

FIELD: information technology.;SUBSTANCE: invention relates to information and computer engineering equipment and can be used for synthesis of arithmetic logic units for designing high-speed and efficient digital devices for summation and subtraction of numbers in a ternary number system in direct codes. The device has a number input and encryption unit, an adder unit, a first number register unit, a second number register unit, a result register unit and a control unit.;EFFECT: reduced hardware expenses, simple combinational circuit and simple algorithm of operation of the device.;18 dwg, 10 tbl