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Arithmetic logic unit for processing binary input signals, has fault detector comparing binary output signals with each other or with inverse output signal to detect error during processing of input signals
Arithmetic logic unit for processing binary input signals, has fault detector comparing binary output signals with each other or with inverse output signal to detect error during processing of input signals
The unit (100) has a processing unit (110) comprising a group of control gates for controlling two processing gates of corresponding two groups of processing gates based on a control signal (mi) to select an algebraic function among a set of algebraic functions. The two groups of processing gates process binary input signals (ai, bi) to obtain two binary output signals, respectively. A fault detector (120) compares the binary output signals with each other or with an inverse output signal to detect an error during processing of the input signals independent of the selected algebraic function. An independent claim is also included for a method for processing binary input signals.
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