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parametrisches scan registers, digital circuit and method for testing a digital circuit using such a register

机译:参数扫描寄存器,数字电路以及使用该寄存器测试数字电路的方法

摘要

The present invention relates to a register scan parametric. It also relates to a method of testing of a digital circuit with the aid of such a register. The register scan, parametric includes a memory cell (21) having at least one data input (d), adapted to receive a datum of the test (e _ scan), and transferring on its output (s), a representative signal (62) of the input data, by means of a synchronization signal (h). It further comprises a block of parametric test (42) whose input is connected to the output (s) of the cell (21), the output signal (62) of the cell being transferred to the output (s _ reg) of the block (42) through an internal module (61), the internal module operating according to the modes able to modify the output signal (62) of the cellule.l' invention applies in particular for the test of integrated circuits with a high integration density, for example in the field of nano-technology.
机译:本发明涉及寄存器扫描参数。它还涉及借助这种寄存器测试数字电路的方法。参数化的寄存器扫描包括具有至少一个数据输入(d)的存储器单元(21),该存储器单元(21)适于接收测试(e_scan)的数据,并在其输出(s)上传送代表信号(62)。通过同步信号(h)来确定输入数据)。它还包括参数测试块(42),其输入连接到单元(21)的输出,单元的输出信号(62)传递到该块的输出(s_reg)。 (42)通过内部模块(61),内部模块根据能够修改小室的输出信号(62)的模式进行操作。1'发明特别适用于具有高集成度的集成电路的测试,例如在纳米技术领域。

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