Automatic performance state transitions in response to processor events

摘要

Automatically transitioning the performance states of components in an integrated circuit comprises a plurality of performance domains each including at least one component, and a power management unit (PMU). The PMU is configured to transition 44 at least one performance domain to a first performance state in response to a processor transitioning 40 to a different performance state (such as low performance or sleep state). The PMU may further transition the performance domain to a second performance state 52 in response to the processor exiting 48 the low performance state. The apparatus may include registers that can be programmed with the one or more performance states of the performance domains and the processor. Timestamps may be recorded 48, 54 at the time of performance domains transition. A performance state may include any combination of performance characteristics for the relevant components, such as a different operating frequency of the provided clock signal and a corresponding supply voltage.