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The standard clock which becomes standard of aforementioned image processing vis-a-vis

机译:相对于上述图像处理成为标准的标准时钟

摘要

PROBLEM TO BE SOLVED: To provide an image processing system, etc. which can execute image processing according to various image modes in a state of simplifying a configuration of an image processing circuit and that of an output circuit for outputting a reference clock or the like to the image processing circuit.;SOLUTION: In the image processing system including the image processing circuit 200 for executing image processing in accordance with an image mode to be used and the output circuit 100 for outputting an image signal to the image processing circuit 200, a control part 110 included in the output circuit 100 determines a frequency value F which is a frequency value not less than a minimum frequency value and not more than a maximum frequency value, expressed by a Hz unit and satisfies a condition of frequency value F=L×M×10n as a reference clock frequency (provided that, n is an integer ≥1, L is a value obtained by multiplying a positive integer value which is not a multiple of 2 and is not a multiple of 5 by all values of at least one of 7, 9, 11, 13, 17, and 19 which are not the positive integer value, and M is an integer ≥1).;COPYRIGHT: (C)2009,JPO&INPIT
机译:解决的问题:提供一种图像处理系统等,其可以在简化图像处理电路和用于输出参考时钟等的输出电路的配置的状态下根据各种图像模式执行图像处理。解决方案:在图像处理系统中,包括:图像处理电路200,用于根据所使用的图像模式执行图像处理;以及输出电路100,用于将图像信号输出至图像处理电路200,输出电路100中包括的控制部110确定频率值F,该频率值F是不小于最小频率值且不大于最大频率值的频率值,以Hz为单位表示并且满足频率值F = L× M× 10 n 作为参考时钟频率(假设n是整数≥ 1,L是通过将正整数值w乘以得到的值hich不是7,9,11,13,17和19中至少一个的所有值(不是正整数)的2的倍数,也不是5的倍数,M是整数≥ 1 );版权:(C)2009,日本特许厅和INPIT

著录项

  • 公开/公告号JP5051372B2

    专利类型

  • 公开/公告日2012-10-17

    原文格式PDF

  • 申请/专利权人 セイコーエプソン株式会社;

    申请/专利号JP20070335741

  • 发明设计人 富田 憲一郎;

    申请日2007-12-27

  • 分类号H04N5/06;

  • 国家 JP

  • 入库时间 2022-08-21 17:42:00

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