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摘要

PROBLEM TO BE SOLVED: To achieve reliable data transfer by exactly distinguishing a regular signal and noises.;SOLUTION: This interface circuit 22 synchronizes to clock generated by a first device (for example, CPU 11) and transmits/receives a signal between the first device and a second device (for example, MEM 20). The interface circuit comprises a phase control part (for example, a delay element 221) which delays the phase of the clock by predetermined time, and a signal creation part (for example, a D type flip-flop 222 with a set/reset terminal) which creates a timing signal to determine whether or not the signal created/output by the second device is a regular synchronizing signal based on the clock output by the phase control part.;COPYRIGHT: (C)2008,JPO&INPIT