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Packet switch, scheduling apparatus, waste control circuit, multicast control circuit, and QoS control device
Packet switch, scheduling apparatus, waste control circuit, multicast control circuit, and QoS control device
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机译:分组交换,调度装置,浪费控制电路,组播控制电路和QoS控制装置
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摘要
To achieve QoS control, drop control and multicast control of a variable-length packet at high speed in small scale hardware, a packet divider divides a variable-length packet into fixed-length packets, and an input buffer section stores the divided fixed-length packets into queues by output lines and by QoS classes. A large number of QoS classes are mapped into only two kinds of classes including a guaranteed bandwidth class for which an assigned bandwidth is guaranteed and a best effort class for which a surplus bandwidth is allocated, thereby to achieve scheduling at the input side by an inter-line scheduler. An output buffer section assembles a variable-length packet from fixed-length packets that have been obtained by switching at a switch section in an output buffer section. A QoS control is performed based on a packet length. IMAGE
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