首页> 外国专利> METHOD FOR EVALUATING IMPURITY DISTRIBUTION UNDER GATE ELECTRODE WITHOUT DAMAGING SILICON SUBSTRATE

METHOD FOR EVALUATING IMPURITY DISTRIBUTION UNDER GATE ELECTRODE WITHOUT DAMAGING SILICON SUBSTRATE

机译:无损伤硅基质的栅电极下杂质分布评估方法

摘要

A method of manufacturing a semiconductor device forms the semiconductor device in a device region of a semiconductor substrate simultaneously with forming a monitor semiconductor device that includes a gate electrode made of silicon containing material arranged on a gate insulating film in a monitor region of the semiconductor substrate, a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. The gate electrode is removed without removing a gate insulating film by applying pyrolysis hydrogen generated by pyrolysis on the monitor semiconductor device in the monitor region, and the gate insulating film is removed by a wet process. Impurities distribution of a silicon active region appearing after the gate electrode is removed is measured and fed back to a semiconductor manufacturing process.
机译:一种制造半导体器件的方法,同时在形成监测器半导体器件的同时在半导体衬底的器件区域中形成半导体器件,该监测器半导体器件包括由含硅材料制成的栅电极,该栅电极布置在半导体衬底的监测器区域中的栅极绝缘膜上。在栅电极的对应侧上形成在半导体衬底上的源电极和漏电极。通过在监视区域中的监视半导体器件上施加由热解产生的热解氢来去除栅电极而不去除栅绝缘膜,并且通过湿法去除栅绝缘膜。测量在去除栅电极之后出现的硅有源区的杂质分布,并将其反馈给半导体制造工艺。

著录项

  • 公开/公告号US2012181671A1

    专利类型

  • 公开/公告日2012-07-19

    原文格式PDF

  • 申请/专利权人 KAZUO HASHIMI;HIDEKAZU SATO;

    申请/专利号US201213429804

  • 发明设计人 HIDEKAZU SATO;KAZUO HASHIMI;

    申请日2012-03-26

  • 分类号H01L23/544;

  • 国家 US

  • 入库时间 2022-08-21 17:34:36

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