COMPENSATION OF PHASE LOCK LOOP (PLL) PHASE DISTRIBUTION CAUSED BY POWER AMPLIFIER RAMPING

摘要

Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.