首页> 外国专利> Pixel layout structure for raising capability of detecting amorphous silicon residue defects and method for manufacturing the same

Pixel layout structure for raising capability of detecting amorphous silicon residue defects and method for manufacturing the same

机译:用于提高检测非晶硅残留缺陷的能力的像素布局结构及其制造方法

摘要

Disclosed is a pixel layout structure capable of increasing the capability of detecting amorphous silicon (a-Si) residue defects and a method for manufacturing the same. Wherein, an a-Si dummy layer is disposed on either one side or both sides of each data line. The design of such an a-Si dummy layer is utilized, so that in an existing testing conditions (by making use of an existing automatic array tester in carrying out the test), in case that there exists an a-Si residue in a pixel, the pixel having defects can be detected through an enhanced capacitance coupling effect and an electron conduction effect. Therefore, through the application of the above-mentioned design, the capability of an automatic array tester can effectively be increased in detecting a defective pixel having a-Si residues.
机译:公开了一种能够提高检测非晶硅(a-Si)残留缺陷的能力的像素布局结构及其制造方法。其中,a-Si虚拟层设置在每条数据线的一侧或两侧。利用这种a-Si虚设层的设计,使得在现有的测试条件下(通过使用现有的自动阵列测试仪进行测试),在像素中存在a-Si残留物的情况下因此,可以通过增强的电容耦合效应和电子传导效应来检测具有缺陷的像素。因此,通过上述设计的应用,可以有效地提高自动阵列测试仪在检测具有a-Si残留的缺陷像素中的能力。

著录项

  • 公开/公告号US8159627B2

    专利类型

  • 公开/公告日2012-04-17

    原文格式PDF

  • 申请/专利权人 WEI-CHUAN LIN;LUNG-CHUAN CHANG;

    申请/专利号US20090405805

  • 发明设计人 LUNG-CHUAN CHANG;WEI-CHUAN LIN;

    申请日2009-03-17

  • 分类号G02F1/1333;

  • 国家 US

  • 入库时间 2022-08-21 17:28:39

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