首页>
外国专利>
Error-tolerant multi-threaded memory systems with reduced error accumulation
Error-tolerant multi-threaded memory systems with reduced error accumulation
展开▼
机译:具有减少错误累积的容错多线程存储系统
展开▼
页面导航
摘要
著录项
相似文献
摘要
Systems and methods establishing and/or utilizing an error-tolerant multithreaded register file are provided. The systems and methods employ dynamic multithreading redundancy (DMR) for error correction. Non-overlapped register access patterns associated create hardware redundancy dynamically that is exploited for error control. Immediate write-back and self-recovery techniques are employed to further enhance the error correction functionalities of the disclosed systems and methods. Error control is improved for memory components and processing functions in multithreaded computing systems.
展开▼