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Digital phase-locked loop circuit including a phase delay quantizer and method of use
Digital phase-locked loop circuit including a phase delay quantizer and method of use
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机译:包括相位延迟量化器的数字锁相环电路及其使用方法
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摘要
A phase locked loop circuit in accordance with an embodiment implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, high bandwidth, and high attenuation digital filter as well. The digital PLL circuit takes advantage of the deep sub-micron process technology which features high speed, high resolution, compact size, and low power.
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