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Restoring plural instructions for same cycle execution from partial instructions and combined supplementing portions generated for compact storage
Restoring plural instructions for same cycle execution from partial instructions and combined supplementing portions generated for compact storage
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机译:从为紧凑存储而生成的部分指令和组合补充部分中恢复用于同一周期执行的多个指令
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摘要
An original first instruction word (I1) to an original third instruction word (I3) include a bit field (L11) and a bit field (L12) to a bit field (L31) and a bit field (L32). An information word (IW) includes a set of some of bit fields belonging to a plurality of instruction words executed in the same cycle, which are the bit field (L12) of the original first instruction word (I1) to the bit field (L32) of the original third instruction word (I3). An instruction decoder (103) of a processor (100) decomposes the information word (IW) and restores the arrangements of the original first instruction word (I1) to the original third instruction word (I3) by combining the bit field (L11) to the bit field (L31) to the bit field (L12) to the bit field (L32). This can reduce the amount of memory consumption without degrading the instruction execution performance.
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