DEVICE FOR ALGEBRAIC COMPARISON OF TWO NUMBERS IN THE RESIDUE CLASS

摘要

A device for algebraic comparison of two numbers in the residue class (RC) whereto the fourth, fifth, sixth and seventh AND gates, the third, fourth and fifth OR gates, the first, second and third AND gates are introduced. The output of position of a positive number attribute of the first input register and output of position of a positive number attribute of the second register are connected to inputs of the fourth AND gate, which output is connected to the first inputs of the first AND gates of the first, second and the third groups. The output of position of the negative number attribute of the first input register and output of position of the positive number attribute of the second input register are connected to inputs of the fifth AND gate, which output is connected to the first inputs of the second AND gate of the first, second and the third groups. The output of position of the positive number attribute of the first input register and output of position of the negative number attribute of the second register are connected to inputs of the sixth AND gate, which output is connected to the first inputs of the third AND gate of the first, second and the third groups. The output of position of the negative number attribute of the first input register and output of position of the negative number attribute of the second input register are connected to inputs of the seventh AND gate, which output is connected to the first inputs of the fourth AND gate of the first, second and third groups. The output of the first AND gate is connected to the second inputs of AND gates of the first group, the output of the first OR gate is connected to the second inputs of AND gates of the second group, the output of the second OR gate is connected to the second inputs of AND gates of the third group, the outputs of the first and the fourth AND gates through the third OR gate are connected to the firstoutput of the device, the output of the third AND gate of the first group, the outputs of the first and the third AND gate of the second group as well as outputs of the third and the fourth AND gate of the third group through the fourth OR gate are connected to the secondoutput of the device, the output of the second AND gate of the first group, the outputs of the second and the fourth AND gates of the second group as well as outputs of the first and the second AND gates of the third group through the fifth OR gate are connected to the thirdoutput of the device.