HARDWARE QUADRATIC PROGRAMMING SOLVER AND METHOD OF USE

摘要

A quadratic programming solver architecture comprising: a first hardware block arranged to perform parallel dot-product operations and thereby carry out matrix-vector multiplication, the first hardware block comprising a plurality of parallel multipliers and an adder tree arranged to combine the outputs from the parallel multipliers; a second hardware block comprising arithmetic processing means arranged to receive input data comprising constants and variables and to perform scalar operations thereon, the output from the arithmetic processing means being arranged to supply the parallel multipliers of the first hardware block, the variables being output from the first hardware block and fed back to the second hardware block; and control means configured to selectively schedule the sequence of scalar operations performed by the arithmetic processing means.