PARALLEL COMPUTATION DEVICE, PARALLEL COMPUTATION METHOD, AND PARALLEL COMPUTATION PROGRAM

摘要

Speed-up of parallel processing performed by a multi-core processor is achieved.;Computational unit area selecting means (1aa, 1ba, ..., and 1na), each of which is provided in individual multiple cores (1a, 1b, ..., and 1n), sequentially select uncomputed computational unit areas in a computational area (4). Computing means (1ab, 1bb, ..., and 1nb), each of which is provided in the individual multiple cores (1a, 1b, ..., and 1n), perform computation for the selected computational unit areas. In addition, the computing means (1ab, 1bb, ..., and 1nb) write computational results (2a, 2b, ...) in a memory device (2) which is accessible from each of the multiple cores (1a, 1b, ..., and In). Computational result transmitting means (1nc) of the core (1n) performs computational result acquisition and transmission processing in a different time period with respect to each of multiple computational result transmission areas (4a, 4b, 4c, and 4d). The computational result acquisition processing is for acquiring, from the memory device (2), computational results related to the computational result transmission areas (4a, 4b, 4c, and 4d).