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Low power processor system having victim cache for filter cache and driving method thereof

机译:具有用于过滤器高速缓存的牺牲者高速缓存的低功率处理器系统及其驱动方法

摘要

PURPOSE: A low power processor system having a victim cache for a filter cache is provided to reduce the number of instruction usages by using the victim cache to lower power consumption. CONSTITUTION: An instruction filter cache(130) is placed between a processor core(110) and an instruction cache(120). If the instruction of the processor core exists, the instruction filter cache draws the instruction prior to the instruction cache. If the instruction requested in the processor core is not stored, the instruction filter cache stores the instruction which is drawn to the processor core from the instruction cache. A victim cache for a filter cache(140) stores the instruction which is deleted from the instruction cache by the instruction which is stored to the instruction filter cache.
机译:目的:提供一种低功耗处理器系统,该系统具有用于过滤器缓存的受害者缓存,以通过使用受害者缓存来降低功耗来减少指令的使用次数。组成:指令过滤器缓存(130)被放置在处理器内核(110)和指令缓存(120)之间。如果存在处理器内核的指令,则指令过滤器高速缓存在指令高速缓存之前绘制指令。如果未存储在处理器内核中请求的指令,则指令过滤器缓存将存储从指令缓存中提取到处理器内核的指令。过滤器高速缓存器(140)的受害者高速缓存器存储通过被存储到指令过滤器高速缓存器中的指令从指令高速缓存器中删除的指令。

著录项

  • 公开/公告号KR101086460B1

    专利类型

  • 公开/公告日2011-11-25

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20090132149

  • 发明设计人 김철홍;박영진;

    申请日2009-12-28

  • 分类号G06F1/32;G06F12;G06F9/06;G06F9/30;

  • 国家 KR

  • 入库时间 2022-08-21 17:11:06

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