FPGA VERIFICATION METHODOLOGY SYSTEM IN THE DISTRIBUTED SIMULATION AND EMULATOR ENVIRONMENT

摘要

PURPOSE: An FPGA design verification system in a distributed surrounding interlinking FPGA development environment is provided to prevent hardware restriction by inspecting the design of FPGA through FPGA development environments. CONSTITUTION: A verification server(100) is connected to a board having an FPGA(Field Programmable Gate Array). A first client(110) is connected through a distributed network to the verification server and emulates a design circuit. A second client(120) is connected through the distribute network to the verification server and simulates the logic operation of a semiconductor. A third client(130) is connected to an online certificate status protocol server through the distributed network.