METHOD OF COMPENSATING JITTERS DUE TO POWER SUPPLY VARIATION AND DIGITALLY CONTROLLED OSCILLATOR IMPLEMENTED THEREOF

摘要

The present invention consists of a pseudo-differential amplifier (pseudo-differential pair) and latch the PMOS and NMOS ( By forming the latch), the variation of the supply voltage on both the rising and falling edges to minimize the propagation delay jitter by compensating symmetrically. The present invention takes the two nodes in the delay line into the amount (delay line) for rough tuning (coarse tuning) constituting the block, and for the fine-tuning, in response to fluctuations in the power supply compensates for the strength of the delay feedback latch of the cell which provides a method. When the present invention is the power supply V _DD is increased to augment the driving force of the PMOS, so the output voltage is increased, the increase in the output voltage is much delay to reverse the previous state and to strengthen the NMOS latch closed Since this may be causing a constant overall propagation delay. As a result, the power supply voltage may be even a slight variation of the constant frequency oscillator clock with no jitter noise.