Barrier layer field effect transistor arrangement comprises node which is provided as drain terminal of arrangement, where another node is provided as source terminal of arrangement, where third node is provided as gate terminal

摘要

The barrier layer field effect transistor arrangement (100) comprises a node (101) which is provided as a drain terminal of the arrangement. Another node (102) is provided as a source terminal of the arrangement. Third node (103) is provided as a gate terminal of the arrangement. A capacitor (30) is arranged between the fourth node (104) and the third node. A field effect transistor (20) is a metal-oxide-semiconductor field-effect transistor.