PROBLEM TO BE SOLVED: To provide a multiphase clock generation circuit that accommodates a plurality of operating frequencies while dispensing with an increase in circuit scale and keeping jitter characteristics of output signals intact.;SOLUTION: The multiphase clock generation circuit includes: a plurality of delay paths adapted to receive a plurality of reference clock signals out of phase and provided for a plurality of frequencies available for the reference clock signals, respectively, which generate a predetermined phase difference to the reference clock signals; a switch section for selecting the delay path corresponding to the frequency of the reference clock signals from the plurality of delay paths on the basis of the frequency of the reference clock signals; and a phase interpolation circuit for generating a plurality of clock output signals having the predetermined phase difference from the plurality of reference clock signals with the phase difference modified by the delay path selected by the switch section.;COPYRIGHT: (C)2013,JPO&INPIT
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