The design method random error generator, and M-sequence generator

摘要

An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(alpha1k), (alpha2k), (alpha3k), . . . } falls within a maximum period (2m-1), the group being produced as an element (alphak) obtained by raising a root alpha of a polynomial to a specified power value k (k=2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (alphak) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (alphak), the gate supplies the multiplication result as feedback bit data to the respective registers.