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CLOCK GENERATOR WITH INTEGRATED PHASE OFFSET PROGRAMMABILITY
CLOCK GENERATOR WITH INTEGRATED PHASE OFFSET PROGRAMMABILITY
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机译:具有集成相移可编程性的时钟发生器
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摘要
A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.
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