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Method and Apparatus of Minimizing Extrinsic Parasitic Resistance in 60GHz Power Amplifier Circuits
Method and Apparatus of Minimizing Extrinsic Parasitic Resistance in 60GHz Power Amplifier Circuits
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机译:使60GHz功率放大器电路中的外部寄生电阻最小化的方法和装置
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摘要
Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.
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