SYNCHRONIZING GLOBAL CLOCKS IN 3D STACKS OF INTEGRATED CIRCUITS BY SHORTING THE CLOCK NETWORK

摘要

There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.