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PROCESSOR AND DATA PROCESSING METHOD INCORPORATING AN INSTRUCTION PIPELINE WITH CONDITIONAL BRANCH DIRECTION PREDICTION FOR FAST ACCESS TO BRANCH TARGET INSTRUCTIONS
PROCESSOR AND DATA PROCESSING METHOD INCORPORATING AN INSTRUCTION PIPELINE WITH CONDITIONAL BRANCH DIRECTION PREDICTION FOR FAST ACCESS TO BRANCH TARGET INSTRUCTIONS
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机译:包含条件分支方向预测的指令管道以快速访问分支目标指令的处理器和数据处理方法
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摘要
Disclosed are a processor and a processing method incorporating an instruction pipeline with direction prediction (i.e., taken or not taken) for conditional branch instructions. In the embodiments, reading of a branch instruction history table (BHT) and a branch instruction target address cache (BTAC) for branch direction prediction occurs in parallel with the current instruction fetch in order to minimize delay in the next instruction fetch. Additionally, direction prediction is performed in the very next clock cycle based either on an initial direction prediction for the specific instruction, as stored in the BHT, or, if applicable, on a prior entry for the specific instruction in the BTAC. An override bit associated with each entry in the BTAC is the determining factor for whether or the BTAC or BHT is controlling. Override bits in the BTAC can be pre-established based on the branch instruction type in order to ensure prediction accuracy.
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