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SYSTEMS AND METHODS FOR 1553 BUS OPERATION SELF CHECKING
SYSTEMS AND METHODS FOR 1553 BUS OPERATION SELF CHECKING
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机译:用于1553公交车运行自检的系统和方法
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摘要
Systems and methods for 1553 bus operation self checking are provided. In one embodiment, a fault tolerant computer comprises a self-checking processor pair that includes a master processor, a checking processor, and self-checking pair logic; a 1553 bus transceiver; and a device comprising 1553 self-checking logic coupled between the self-checking processor pair and the 1553 bus transceiver, wherein the 1553 self-checking logic manages data communication between the 1553 bus transceiver and the self-checking processor pair. The 1553 self-checking logic includes a primary logic and a secondary logic that operate in lock-step. When the 1553 self-checking logic writes data to the 1553 bus transceiver, the 1553 self-checking logic compares a first 1553 formatted message generated by the primary logic to a second 1553 formatted message generated by the secondary logic, and generates an error indication when the first 1553 formatted message does not match the second 1553 formatted message.
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