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Suppressing power supply noise using data scrambling in double data rate memory systems

机译:在双倍数据速率存储系统中使用数据加扰抑制电源噪声

摘要

Embodiments are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.
机译:实施例大体针对用于在双倍数据速率存储系统中使用数据加扰来抑制电源噪声的系统,方法和装置。在一些实施例中,集成电路包括传输数据路径以将数据传输到一个或多个存储设备。发射数据路径可以包括加扰逻辑,以并行地生成彼此不相关的N个伪随机输出。输出数据和伪随机输出被输入到XOR逻辑。发射数据路径发射具有基本上白色频谱的XOR逻辑的输出。描述和要求保护其他实施例。

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