Timing verification method for deterministic and stochastic networks and circuits

摘要

The timing verification method for deterministic and stochastic networks and circuits is a computerized method that includes a non-enumerative path length analysis algorithm for deterministic and stochastic directed acyclic graphs (DAGs) with applications to timing verification of circuits, the algorithm computing statistical measures of path lengths without storing and/or manipulating the paths in such networks. The timing verification method is able to compute deterministic or probabilistic costs assigned to edges, vertices, or both.