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G-ODLAT on-die logic analyzer trigger with parallel vector finite state machine
G-ODLAT on-die logic analyzer trigger with parallel vector finite state machine
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机译:具有并行矢量有限状态机的G-ODLAT管芯逻辑分析仪触发器
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摘要
An apparatus for debugging internal signals of integrated circuits is presented. In one embodiment, the apparatus comprises a number of vector registers associated with states of a state machine. A group of registers, associated with a state of the state machine, comprises a mask register an arm register. A comparator compares debug data with contents of the mask register and the arm register to determine a comparison result to be stored in one or more bit positions of the vector register. The apparatus further comprises a triggering logic unit to determine whether or not to trigger a fire event based on the vector registers.
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