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HIGH PERFORMANCE TURBO AND VITERBI CHANNEL DECODING IN DIGITAL SIGNAL PROCESSORS
HIGH PERFORMANCE TURBO AND VITERBI CHANNEL DECODING IN DIGITAL SIGNAL PROCESSORS
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机译:数字信号处理器中的高性能涡轮和维特比通道解码
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摘要
A digital signal processor (110) performs turbo and Virterbi channel decoding in wireless systems. The computation blocks (112, 114) of the digital signal processor (110) are provided with an accelerator for executing instructions associated with trellis computations. An ACS instruction performs trellis computations of alpha and beta metrics. Multiple butterfly calculations can be performed in response to a single instruction. A TMAX instruction is used to calculate the log likelihood ratio of the trellis.
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