WIDE RANGE CHARGE BALANCING CAPACITIVE-TO-DIGITAL CONVERTER

摘要

A capacitive-to-digital converter is provided which includes: sensor, offset and reference capacitors, an integrator circuit and a demodulation circuit. The sensor capacitor is switched according to a first clock and the offset capacitor according to a second clock, which has a higher switching frequency. The reference capacitor is switched according to a return signal from the converter's output. The integrator circuit includes an integrator capacitor, and has first and second nodes, with the sensor, offset and reference capacitors each being switched to the first and second nodes based on the respective first clock, second clock or return signal. The demodulation circuit receives and converts output of the integrator circuit into a digital output. The higher frequency clocking of the offset capacitor allows for a reduction in capacitance of the offset, reference or integrator capacitor, and the multiclocking of the converter allows for use of a multireferencing to the sensor capacitor.