WIDE INPUT BIT-RATE, POWER EFFICIENT PWM DECODER

摘要

A pulse width modulated (PWM) signal (RXDATA) is received and, over a time interval (Tb) of the PWM signal, a first count (402A) is incremented when the PWM signal is at a first level (low), and a second count (402B) is incremented when the PWM signal is at a second level (high). At the end of time interval the first count is compared (416) to the second count and, based on the comparison, a decoded bit (DataOut)is generated. Optionally, incrementing the first count (402A) is by enabling a first oscillator that increments a first counter (412A), and incrementing the second count (402B) is by enabling a second oscillator that increments a second counter (412B).