PROCESSOR BASED ON A SWIZZED VIRTUAL REGISTER AND A SWIZZLE PATTERN PROVIDING DEVICE THEREOF CAPABLE OF REDUCING UNNECESSARY OVERHEAD CAUSED BY THE EXECUTION OF A SWIZZLE INSTRUCTION

摘要

PURPOSE: A processor based on a swizzed virtual register and a swizzle pattern providing device thereof are provided to improve the performance of the processor by reducing the number of swizzle instructions generated during application execution. CONSTITUTION: A vector register(102) stores a data set related to vector operation. A swizzle pattern providing unit(103) provides a swizzle pattern about the data set of the vector register. The swizzle pattern providing unit combines each data element of the data set about the vector register or changes an arrangement sequence of the data elements. The swizzle pattern providing unit combines each data element of the data set about first and second vector registers. The swizzle pattern providing unit includes data lines connected with the input of a vector calculating unit(101). [Reference numerals] (101) Vector calculating unit