PURPOSE: An ECO logic cell and a method for changing a design using the same are provided to reduce the cost of design change. CONSTITUTION: An input node(21,22) receives an input signal. An output node(23) outputs the result of logic operation according to the input signal. An active layer includes the drain and the source region of a transistor. A polysilicon layer includes a gate region of the transistor. A metal layer electrically connects the polysilicon layer to the active layer, the input node or the output node.
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