Method for manufacturing wafer of integrated circuit, involves extending doped area along lower edges from vertical gate to form source area in transistors of cell memories so that transistors comprise channel areas

摘要

The method involves producing a vertical gate (SGC) in a semiconductor substrate (PW), and establishing a doped area, which is formed as an insulating layer (NISO). The doped area is extended along two lower edges from the vertical gate to form a source area (S) in two selection transistors (ST31, ST32) of two cell memories such that the selection transistors of the cell memories comprise two channel areas (CH2) between another doped area i.e. drain area (n2), and the former doped area, where the channel areas are vertically extended on sides of the vertical gate. An independent claim is also included for an integrated circuit.