The electric potential revision method null in the latched circuit and the

摘要

This invention, jointing with the CML buffer of the latter part, offers the operational possible latched circuit to high speed. The 1st and 2nd entry terminal and the output terminal and, signal level of the 1st and 2nd entry terminal when it is each one 1st and 2nd level Drive the output terminal in 1st level, signal level of the 1st and 2nd entry terminal directing the output terminal to 2nd level when it is each one 2nd and 1st level, Drive, the Drive circuit and the output terminal which when signal level of the 1st and 2nd entry terminal is the respective 1st level control the output terminal in floating stateDirecting to 2nd level, signal level of the output terminal the limiting circuit which is restricted in 3rd level between 1st and 2nd level and, is had when Drive (drawing 1).