首页> 外国专利> SELECTIVE FAULT STALLING FOR A GPU MEMORY PIPELINE IN A UNIFIED VIRTUAL MEMORY SYSTEM

SELECTIVE FAULT STALLING FOR A GPU MEMORY PIPELINE IN A UNIFIED VIRTUAL MEMORY SYSTEM

机译:统一虚拟内存系统中GPU内存管道的选择性故障安装

摘要

One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a selective fault-stalling pipeline. Upon detecting a memory access fault associated with an operation executing on a particular SM, a replay unit in the selective fault-stalling pipeline considers the operation as a faulting operation. Subsequently, instead of notifying the SM of the memory access fault, the replay unit recirculates the operation—reinserting the operation into the selective fault-stalling pipeline. Recirculating faulting operations in such a fashion enables the SM to execute other operation while the replay unit stalls the faulting request until the associated access fault is resolved. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a memory access fault, cancel the associated operation and subsequent operations.
机译:本发明的一个实施例是一种并行处理单元(PPU),其包括一个或多个流式多处理器(SM)并实现选择性的故障跟踪管线。在检测到与在特定SM上执行的操作相关联的存储器访问故障时,选择性故障跟踪管线中的重放单元将所述操作视为故障操作。随后,重播单元没有向SM通知内存访问故障,而是重新循环了操作-将操作重新插入到选择性故障跟踪管道中。以这种方式再循环故障操作使SM能够执行其他操作,同时重放单元将故障请求暂停,直到解决了相关的访问故障。有利地,与传统的PPU相比,PPU的整体性能得到了改善,后者在检测到存储器访问故障时取消了关联的操作和后续操作。

著录项

  • 公开/公告号US2014281679A1

    专利类型

  • 公开/公告日2014-09-18

    原文格式PDF

  • 申请/专利权人 NVIDIA CORPORATION;

    申请/专利号US201314109686

  • 发明设计人 OLIVIER GIROUX;SHIRISH GADRE;

    申请日2013-12-17

  • 分类号G06F11/20;

  • 国家 US

  • 入库时间 2022-08-21 16:09:30

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