A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit at a first level higher than a second level at which design verification and/or design simulation of the electronic circuit is to be conducted, and representing instances of elements of the electronic circuit in a data structure. The method also includes parsing, at the first level, the design to automatically generate a list of regular expressions related to text-matching strings with the elements of the electronic circuit based on removing undesired instances related to the elements from the data structure, and pruning, at the second level, connectivity descriptors of the electronic circuit based on the automatically generated list of regular expressions. Further, the method includes optimizing the design verification and/or the design simulation at the second level based on the pruned connectivity descriptors thereof.
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