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Dynamic adaptation of continuous time linear equalization circuits

机译:连续时间线性均衡电路的动态自适应

摘要

An embodiment of the invention includes dynamically adjusting gain peaking of circuit logic such that error rates are acceptable across various process/voltage/temperature (PVT) ranges. An embodiment uses PVT dependant programming, such as but not limited to resistance compensation (RCOMP) codes, to control impedance compensation logic, such as but not limited to a Continuous Time Linear Equalization (CTLE) circuit. The PVT programming may be used to control gain peaking amplitude and gain peaking frequency across ranges of different PVTs. As a result, error performance is not impaired across different PVT corners and gain peaking is more consistent across different PVT corners. Other embodiments are included herein.
机译:本发明的实施例包括动态地调整电路逻辑的增益峰值,使得在各种过程/电压/温度(PVT)范围内误差率是可接受的。实施例使用诸如但不限于电阻补偿(RCOMP)代码之类的PVT相关编程来控制阻抗补偿逻辑,诸如但不限于连续时间线性均衡(CTLE)电路。 PVT编程可用于控制不同PVT范围内的增益峰值幅度和增益峰值频率。结果,在不同的PVT拐角处的错误性能不会受到损害,并且在不同的PVT拐角处的增益峰值更加一致。本文包括其他实施例。

著录项

  • 公开/公告号US8872541B2

    专利类型

  • 公开/公告日2014-10-28

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201313746147

  • 发明设计人 SUBRATAKUMAR MANDAL;

    申请日2013-01-21

  • 分类号H03K17/16;H03H7/38;

  • 国家 US

  • 入库时间 2022-08-21 16:03:50

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