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Methods to reduce output voltage ripple in constant on-time DC-DC converters

机译:减少恒定导通时间DC-DC转换器中输出电压纹波的方法

摘要

According to one aspect of the teachings herein, a DC-to-DC converter operates according to an advantageous constant on-time topology that reduces output voltage ripple during light load conditions. The converter produces an output voltage by driving high-side and low-side switches in an inductor-based switching circuit, and regulates the output voltage by varying the on-time of a low-side switch, while holding the on-time of the high-side switch constant. Advantageously, the converter shortens the on-time of the high-side switch during light load conditions, which reduces the output voltage ripple. Thus, the converter may be understood as using a first, constant on-time for the high-side switch during “normal” operations and a second, shorter on-time for the high-side switch during light load conditions.
机译:根据本文的教导的一个方面,DC-DC转换器根据有利的恒定导通时间拓扑来操作,该拓扑降低了轻载条件下的输出电压纹波。转换器通过驱动基于电感器的开关电路中的高侧和低侧开关来产生输出电压,并通过改变低侧开关的导通时间来调节输出电压,同时保持其导通时间。高端开关常数。有利地,该转换器缩短了轻载条件下高端开关的导通时间,从而减小了输出电压纹波。因此,该转换器可以被理解为在“正常”操作期间对于高端开关使用第一恒定的接通时间,并且在轻负载条件下对于高端开关使用第二较短的接通时间。

著录项

  • 公开/公告号US8773099B2

    专利类型

  • 公开/公告日2014-07-08

    原文格式PDF

  • 申请/专利权人 STEVEN M. GRANGER;

    申请/专利号US201113197326

  • 发明设计人 STEVEN M. GRANGER;

    申请日2011-08-03

  • 分类号H02M3/156;

  • 国家 US

  • 入库时间 2022-08-21 16:00:48

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