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Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register
Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register
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机译:执行带有元素大小控制位的指令,以将源寄存器的一半打包数据元素交错存储在相同大小的目标寄存器中
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摘要
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
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