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process for preparation of digital signals for the transmission / reception of a stream of digital signals on a cultural of channels

机译:准备用于在文化通道上发送/接收数字信号流的数字信号的过程

摘要

Method for processing digital signals for transmission/reception from a transmitter (TX) to a receiver (RX) via a transmission management module (GTX) and a reception management module (GRX), on/by a plurality (N) of channels (C i ) with a respective capacity (c i ), of a data stream (F TX ) comprising, in a time unit (T), an assigned quantity of basic units (Uj) of digital signals not greater than the sum (C TOT ) of the individual transmission capacities (c i ) of the channels (C i ), said transmission/reception being regulated by a system clock (CKS) and by an enable signal (En) able to generate a clock signal (CKSEn) with smaller fronts compared to the system clock (CKS), the method comprising the following steps: - defining a derived clock signal (CKSEn - CKS&En), comprising the fronts of the system clock (CKS) derived from enabling of the Enable signal (En); - defining a derived Enable signal (CKSEn/N) obtained from division by N of the fronts of the derived clock signal (CKSEn); - defining N status counters (Cont i ), each associated with a corresponding channel C i , which count for c i up to c max ,; - defining N overflow registers (Ovf i ) with binary values (0/1) each associated with a corresponding channel C i ; - defining a channel counter (CONTN) which assumes the sequence of values 0,1,2... , N-1; - defining N synchronization signals SYNC i each designed to enable sending of the units Uj to the corresponding channel C i ; - initializing the system at a time unit clock (CKU) by setting: all the status counters Cont i = 0, all the overflow signals Ovf i = 0, the channel counter ContN = 0, all the signals SYNCi = 0 - incrementing at each front of the derived clock signal (CKSEn) enabled by the derived enable signal (CKSEn/N) the value of each channel counter ((Cont i ) by the value c i equal to the existing capacity of the channel C i ; - if Cont i ‰¥c max forcing Cont i =Cont i -c max , and - forcing the overflow signal of the channel C i to 1, O V f i =1 - incrementing by one unit the value of the channel counter (ContN) at each front of the derived clock signal (CKSEn); - activating the signal SYNC i if the channel C i corresponding to the existing value of the channel counter (ContN) is in overflow, i.e. Ovf i =1, - generating a signal (SyncTX;SyncRX) for enabling inputting of the data (Uj) from the source (TX;GRX) to the receiver (GTX;RX) able to determine sending of the existing signal Uj on/by the enabled channel C i ,
机译:用于处理数字信号的方法,该数字信号用于通过多个(N)信道(C)经由传输管理模块(GTX)和接收管理模块(GRX)从发射机(TX)到接收机(RX)进行传输/接收i)具有相应容量(ci)的数据流(F TX),该数据流在时间单位(T)中包括分配的数字信号基本单位(Uj)数量,该数量不大于以下之和(C TOT):信道(C i)的各个传输容量(ci),所述传输/接收由系统时钟(CKS)和使能信号(En)来调节,该使能信号(En)能够产生比前者更小的前端的时钟信号(CKSEn)。系统时钟(CKS),该方法包括以下步骤:-定义导出的时钟信号(CKSEn-CKS&En),包括从启用信号(En)的启用导出的系统时钟的前沿(CKS);-定义通过从导出时钟信号(CKSEn)的前沿的N除以获得的导出使能信号(CKSEn / N);-定义N个状态计数器(Cont i),每个状态计数器与对应的信道C i相关联,其对c i进行计数直到c max;-定义N个具有二进制值(0/1)的溢出寄存器(Ovf i),每个二进制值与对应的通道C i相关联;-定义一个信道计数器(CONTN),它假定值序列为0,1,2 ...,N-1;-定义N个同步信号SYNC i,每个同步信号被设计成使得能够将单元U j发送到相应的信道C i;-通过以下方式以时间单位时钟(CKU)初始化系统:所有状态计数器Cont i = 0,所有溢出信号Ovf i = 0,通道计数器ContN = 0,所有信号SYNCi = 0-在由派生的使能信号(CKSEn / N)使能的派生的时钟信号(CKSEn)的每个前端增加每个信道计数器的值((Cont i)),其值ci等于信道C i的现有容量;-如果Cont i≥¥c max强制Cont i = Cont i -c max,并且-强制通道C i的溢出信号为1,O V f i = 1-在所导出的时钟信号(CKSEn)的每个前端将通道计数器(ContN)的值增加一个单位;-如果对应于通道计数器(ContN)的现有值的通道C i溢出,即Ovf i = 1,则激活信号SYNC i;-产生信号(SyncTX; SyncRX)以使得能够将数据(Uj)从源(TX; GRX)输入到接收器(GTX; RX),该信号能够确定在启用的信道C上/由启用的信道C发送现有信号Uj一世 ,

著录项

  • 公开/公告号IT1404184B1

    专利类型

  • 公开/公告日2013-11-15

    原文格式PDF

  • 申请/专利权人 SIAE MICROELETTRONICA S.P.A.;

    申请/专利号IT2011MI00304

  • 发明设计人 CUCCHI DANIELE;

    申请日2011-02-28

  • 分类号H04J3/16;

  • 国家 IT

  • 入库时间 2022-08-21 15:55:42

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