首页>
外国专利>
IMPROVED SPACER DESIGN TO PREVENT TRAPPED ELECTRONS
IMPROVED SPACER DESIGN TO PREVENT TRAPPED ELECTRONS
展开▼
机译:改进的间隔设计可防止陷获的电子
展开▼
页面导航
摘要
著录项
相似文献
摘要
Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices.
展开▼