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A METHOD FOR INCREASING OR DECREASING DUTY CYCLE IN A PULSE-WIDTH-MODULATED VOLTAGE REGULATOR AND A CLOCK OSCILLATOR SYSTEM
A METHOD FOR INCREASING OR DECREASING DUTY CYCLE IN A PULSE-WIDTH-MODULATED VOLTAGE REGULATOR AND A CLOCK OSCILLATOR SYSTEM
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机译:脉宽调制电压调节器中占空比增大或减小的方法及时钟振荡器系统
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摘要
( no cycle skipping ) operating at a fixed frequency duty cycle control of the switching regulator provides a clock oscillator for use system is provided. In one embodiment , the circuit according to the present invention using an analog feedback loop , and extend the switch ON time of the clock cycle by controlling the oscillator charge current , thereby increasing the duty cycle . Preferably , the circuit is very low drop of the very high duty cycle required - out (drop-out) operate on , a very high or a very low duty cycle in the PWM switching regulator operating at different conditions of time required the switching duty cycle, and / or a very low duty cycle switching can be achieved .
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