首页> 外国专利> A METHOD FOR INCREASING OR DECREASING DUTY CYCLE IN A PULSE-WIDTH-MODULATED VOLTAGE REGULATOR AND A CLOCK OSCILLATOR SYSTEM

A METHOD FOR INCREASING OR DECREASING DUTY CYCLE IN A PULSE-WIDTH-MODULATED VOLTAGE REGULATOR AND A CLOCK OSCILLATOR SYSTEM

机译:脉宽调制电压调节器中占空比增大或减小的方法及时钟振荡器系统

摘要

( no cycle skipping ) operating at a fixed frequency duty cycle control of the switching regulator provides a clock oscillator for use system is provided. In one embodiment , the circuit according to the present invention using an analog feedback loop , and extend the switch ON time of the clock cycle by controlling the oscillator charge current , thereby increasing the duty cycle . Preferably , the circuit is very low drop of the very high duty cycle required - out (drop-out) operate on , a very high or a very low duty cycle in the PWM switching regulator operating at different conditions of time required the switching duty cycle, and / or a very low duty cycle switching can be achieved .
机译:(无周期跳变)以固定频率工作的开关调节器的占空比控制提供了用于系统的时钟振荡器。在一个实施例中,根据本发明的电路使用模拟反馈回路,并通过控制振荡器的充电电流来延长时钟周期的开关接通时间,从而增加占空比。优选地,电路在所需的高占空比的非常低的压降下工作(压降),在PWM开关调节器中在不同的时间条件下工作的非常高或非常低的占空比需要开关占空比,和/或可以实现非常低的占空比切换。

著录项

  • 公开/公告号KR101332677B1

    专利类型

  • 公开/公告日2013-11-25

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20087010700

  • 发明设计人 리아오 치아웨이;

    申请日2006-08-07

  • 分类号H02M3/156;H03K4/50;

  • 国家 KR

  • 入库时间 2022-08-21 15:44:13

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