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in parallel device for highly compressed hochgeschwindigkeits-lz77-tokenisierung and huffman coding for deflate compression

机译:在高度压缩的并行设备中用于压缩压缩和霍夫曼编码

摘要

Parallel compression is performed on an input stream by means of a processing circuit. The processing circuit includes a hash-circuit, -tuning-engines, a queue- or pipeline circuit and a by means of coincidence selector. The identified hash-circuit multiple positions in one or more history buffers for searching for target data in the input stream. The lead -tuning-engines parallel multiple search for the target data in the one or more by history buffers. The queuing circuit leads into the queue to search for multiple sequential target data located in the input stream in successive clock cycles by. Then the selected by means of coincidence selector a result of the multiple search for and the search for located in the queue, in order to compress the input stream.
机译:借助于处理电路对输入流执行并行压缩。该处理电路包括散列电路,调谐引擎,队列或流水线电路以及通过巧合选择器。在一个或多个历史缓冲器中所标识的哈希电路的多个位置,用于在输入流中搜索目标数据。前导调整引擎通过历史缓冲区并行搜索一个或多个目标数据。排队电路通入队列以在连续的时钟周期中搜索位于输入流中的多个顺序目标数据。然后通过巧合选择器选择多重搜索的结果和位于队列中的搜索的结果,以便压缩输入流。

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