sampling correction method of asynchronous counter circuit and the asynchronous counter circuit

摘要

PROBLEM TO BE SOLVED: To provide a counter circuit which can output correct count rates even if delays are integrated and races are generated, and also provide a sampling correction method for the counter circuit.;SOLUTION: An embodiment comprises: a counter part 11 to calculate count rates Q0 to QN-1 by counting in accordance with counter clocks CK-DCO; a sampling part 12 to take the count rates with at least three sampling clocks Ref-CK[0], [1], [2]; and a judgment part 13 to judge at least three sampling values SA₀ to SA_N-1, SB₀ to SB_N-1, SC₀ to SC_N-1 taken with the at least three sampling clocks, using timing mismatches in the at least three sampling clocks.;COPYRIGHT: (C)2013,JPO&INPIT