Cache line allocation mechanism of thread units in partitioned shared cache in a multithreaded processor

摘要

System and method for allocation of the cache line in the segmented shared cache of a multithreaded processor (102) (104). Memory management unit (110) is configured to determine the attributes associated with the address of the cache entry associated with the processing thread should be allocated to the cache (T0). Configuration Register (CP 300_0) is configured to store cache allocation information based on the determined attributes. Segment register (DP 310) is configured to store the partitioning information for partitioning the cache into two or more parts (Main / spare Figure 3). Cache entry, based on the configuration register and Segment registers are assigned to one of the portion of the cache.